Due to the delay of EUV lithography, “complementary lithography” is widely considered as a promising solution for continuous IC scaling down to sub-10 nm half pitch [1]. Its patterning process starts from a line/trench fabrication step followed by a line-cut/trench-block step to form the desired 1-D high-density IC patterns [2]. Therefore, a satisfactory edge-placement accuracy of the cut holes is critical for its future success [2]. In particular, the overlay errors and critical-dimension variations presented in the cut-hole patterning process are the main yield-loss factors and there is an urgent need to develop a processing solution to improve the cut-hole patterning yield.
Spacer based self-aligned multiple patterning (SAMP [3-7]) techniques such as self-aligned double (SADP [3]), triple (SATP [4]), quadruple (SAQP [5]), sextuple (SASP [6]), and octuple (SAOP [7]) schemes, when combined with DUV immersion lithography, can potentially drive the minimum half pitch of IC features down to about 5 nm. In a SATP process as shown in FIG. 1 (prior art, [4]), small mandrel lines are patterned first using material A. After the mandrel patterning step, two consecutive spacers as shown in FIG. 1C (i.e., the sacrificial and then structural spacers) are formed on the lateral sides of the mandrel lines. The sacrificial spacers are then etched, leaving the mandrel lines (made of material A) and structural spacers (made of material B) and resulting in spatial frequency tripling. This SATP process allows us to select different materials for mandrel lines and structural spacers (e.g., A B B A B B A B B . . . as shown in FIG. 1D). Therefore, it is possible to apply a highly selective etching process to remove certain type of lines (e.g., made of material A) with negligible loss of the other lines (e.g., made of material B).
For a comparison, one SAQP process scheme reported in the literature [5] is shown in FIG. 2. It starts from a mandrel patterning step (FIG. 2B), followed by a spacer (first spacer or spacer 1) forming process (FIGS. 2C-2D) and an etching process to remove the mandrels (FIG. 2E). After the spacer 1 patterns are transferred to the underneath layer (FIG. 2F), the second spacers (or spacer 2) will be formed on the sidewalls of the transferred/sacrificial lines. These sacrificial lines are then etched and the left patterns are the second spacers made of one single material (see FIG. 2H). Unlike the line features fabricated by a dual-material SATP process, the single-material characteristic of the final SAQP line features does not accommodate a highly selective etching process (in a following step) to partially remove certain exposed lines in the array without attacking other lines that are also exposed.
The self-aligned sextuple patterning (SASP [6]) process can be considered as an extension of the SATP process except that its feature density can be twice of the SATP density. As shown in FIG. 3 (prior art, [6]), a SASP process (see FIGS. 3C-3E) defines the mandrels by the first spacers (possibly by an etching/transfer process) while the mandrels in a SATP process are printed by optical lithography. This can not only increase the feature density, but also result in better critical-dimension (CD) uniformity and line-width-roughness (LWR) performance. Two consecutive spacers (i.e., the second and third spacers) are then formed on the lateral sides of the mandrels while the second/sacrificial spacers are etched and the final line patterns consist of two types of spacers: the first-spacer defined mandrels and third spacers (as shown in FIGS. 3G-3H). The common characteristic of the SATP and SASP processes is that their final lines can be made of two different materials. As we shall describe later, such a material characteristic allows us to design a novel processing method to reduce the effect of edge-placement errors (EPE, defined as the difference between the intended and actual edge locations of holes/trenches over lines [2], [8]) when etching/cutting the exposed lines through the holes on top of them.
In a self-aligned octuple patterning (SAOP [7]) process shown in FIG. 4, three consecutive spacers are formed while the final line patterns consist of only one type of spacers: the third spacers. These spacers are made of one single material (see FIG. 4I) and consequently the SAOP and SAQP processes mentioned above (unlike the SATP or SASP processes) do not allow a selective etching process (in a following step) to partially remove certain exposed lines.
By using the complementary lithography [2], a paradigm shift in device structure and IC design from random 2-D to regular 1-D scenario has occurred recently in the semiconductor industry. As shown in FIG. 5 (prior art [2]), the high-density 1-D grating structure will be first patterned by a SAMP process (FIG. 5A) followed by EUV or other lithographic process (one or multiple exposures) to pattern the cut holes on top of the lines (FIG. 5B). After the cut-hole patterning step, a plasma etching process will be used to remove the exposed parts of the 1-D lines to form desired 1-D circuit patterns (FIG. 5C). However, one critical challenge in complementary lithography is the inaccuracy of hole-edge placement due to the overlay errors (e.g., misalignment) and hole CD variations in the patterning step. For instance, a misaligned hole (on the patterned resist layer) indicated by the dashed rectangle in FIG. 5D can expose a non-targeted line that is supposed to remain unexposed in a following etch process. As a result, this non-targeted line may be mistakenly cut apart provided that it is made of the same material as other targeted lines, thus causing a device/circuit failure due to the loss of electrical connection function. To avoid such a failure in the presence of edge-placement errors, one possible method is to use (two) different materials for the targeted and non-targeted lines and choose a highly selective etching process that can only remove the material of the targeted lines. Even the non-targeted lines may be mistakenly exposed by misaligned holes, a highly selective etching process will not attack the exposed parts (i.e., with negligible material loss) and thus can avoid completely cutting the non-targeted lines apart.
In conclusion, the previously reported single-material SAQP and SAOP processes [5] [7] suffer from the edge-placement errors. They must be modified in order to accommodate two different materials (in an alternating order) in the final patterns for solving the issue of edge-placement errors. The purpose of this patent is to report several new design and fabrication methods that allow such a dual-material type of patterning techniques to reduce the effect of inevitable edge-placement errors in an IC lithographic process.